The present invention relates to improved data processing method, and more specifically, to method for providing preemptive in-pipeline store compare resolution during data processing.
In a computer system, the processor (CPU) executes instructions of a program. Typically, execution of instructions involves fetching (e.g., loading) and reading data into registers from memory (e.g., a cache), performing operations on the data, and storing and writing the results of the operations to memory, for example. Sometimes there may be latency due to a fetch and store simultaneously attempting to access a cache during a same processor cycle, for example, where a store has to wait for the fetch request to access the cache. Other times, the fetch must wait for the store to update the cache, otherwise the fetch may retrieve old data from a shared cache. Due to the nature of the shared cache pipeline, the target store that the fetch is waiting for could actually be ahead of the fetch in the pipeline. The fetch still must detect the store because if it missed seeing a store that is close ahead of it in the pipeline the fetch may retrieve old data from the shared cache or the fetch may stall because not seeing the missed store causes it to become stuck in a state waiting for a store that never comes. One method involves having a fetch request set a wait for the store, and then to look ahead for the store in the shared pipeline and reset the wait if it sees the store. However, this method results in added latency due to the fetch request having to set a wait for a few processor execution cycles for a store that may have already accessed the shared cache. This method also results in increase in area and power usage due to the replication of the logic in many fetch requests.